The present invention relates to an interface device, a method and a monitoring system for providing status information about the status of a hardware device to a plurality of process means. The invention particularly addresses the problem how the status information about the current state of a hardware device can be simultaneously and independently provided to several process means which may each require an access to at least a part of said status information or to the complete status information.
In many applications it is necessary to supervise the state of a hardware device. For example, if the hardware device is a machining apparatus, a control device (e.g. a control computer) needs to know whether the machining tool of the machining apparatus has responded correctly to a command issued by the control device. Therefore, the machining tool outputs a status information to the control device which indicates the current status of the machining tool, i.e. whether it is currently executing a cutting operation, a drilling operation etc. Furthermore, the status information may indicate the positioning of the machining tool with respect to a workpiece.
Furthermore, in most microprocessor controlled hardware devices there is provided a status register into which the hardware device writes the current status information of the hardware device. This is for example of particular importance in multi-tasking systems where it is essential to have an exact knowledge about each task""s current status such that another task is correctly timed.
There is no problem when a status memory is provided into which the status information is written and if there is only one process means (e.g. a computer) which once accesses this status information in the status memory and subsequently processes said status information. Whenever a new status information is written into the status memory the process means can read out the status information and perform the processing thereof, the aim being to detect when a change in the status information has occurred.
As will be explained below with further details, a non-latching or a latching status memory may be used. In a non-latched status memory the status information always exactly reflects the current status of the hardware device, i.e. the status information is not held in the memory up to the next polling timing where the memory is polled. By contrast, in a latching memory the status information is set according to the current status of the hardware device, however, it is held (i.e. latched) in the status memory up to the next polling timing (i.e. rending). After being polled the status information in the status memory is reset and is only set with the next change of the status of the hardware device.
Thus, the polling process means detects the change of a status (i.e. an operation state) of said hardware device even when the state of the hardware device has changed from a state B to state A and back to state A inbetween two polling cycles. This is shown in FIG. 4. When a process mean reads the state before t0 (1. polling cycle) and then at t2 (next polling cycle) the process mean will read state B at both cycles in case of non-latched memory. So the temporary state-A (during t0 to t1) will not be detected.
In case of latched memory the process mean will detect state A at time t2 although the hardware state has already changed back to state B.
The usage of a non-latching memory results in the disadvantage that the process means can not detect the status change described before. As opposed to the usage of non-latching memories, the latched memory has the advantage that the status of the hardware device is at least kept in the memory until the first polling, since after a change of status the information is held in the memory. However, in this case the status information in the memory is reset when a polling is executed such that the information can only be read by one single process means.
The status information itself may be quite complex information and it may be necessary that several independent process means successively or simultaneously access said status information. If for example the status information relates to different operation states of the machining apparatus discussed above, then such status information may contain a first information relating to the xe2x80x9cdrilling statexe2x80x9d, a second information relating to the xe2x80x9ccutting statexe2x80x9d and a third information relating to the xe2x80x9cpositioning statexe2x80x9d. Since the machine tool might be controlled by several independent process means, for example one for the drilling operation and one for the cutting operation, a part of the entire status information relating to the xe2x80x9cpositioning statexe2x80x9d must be accessible by the drilling process means as well as the cutting process means, sequentially or even simultaneously.
Most importantly, the individual independent process means may have different clock rates for access operation, such that accidentally two process means may access the same status information (or a part of it) such that a collision occurs. Furthermore, in case the status memory is based on a latching memory, the status information will be reset by one process means making it impossible for a second process means to read this information again, since it will be reset by the first process means.
Often the state information is set and reset as individual status or indication bits in the memory. They may be set/reset individually or as one word consisting of a number of indication bits at predetermined bit positions in the memory.
FIG. 3 shows the problems described above with more details when individual bits are used as status information in a memory. In FIG. 3 there is shown a hardware device HW which includes an interface device ID through which status information about the status of the hardware device HW is communicated to a monitoring processing device SW which comprises several process means A, B, C. The interface device ID comprises a memory MEM1 with a number m of registers REG11, . . . , REG1m. Each register can hold k indication bits, indicated with a dot. The indications are thus assembled bit-wise in the memory registers. The registers may be latched or non-latched. The three process means A, B, C can access (e.g. via a software access) SAA, SAB, SAC each register of the memory MEM1 to read out the indication bits for further processing. The registers can only be read entirely by the monitoring processing device SW, i.e. its respective process means A, B, C. Assuming k=4 in FIG. 3, this means that always all four bits of a register are read if a register is accessed and if it is a latching register all status information is reset. That is, the hardware device HW continuously writes bits into a register as a part of the complete status information, wherein all bits stored in all registers form the complete current status information about a current status of the hardware device HW. The bits can be independently written and may individually change at different times.
Although in FIG. 3 the interface device ID is shown as being part of the hardware device HW, it may also be situated in the monitoring processing device SW or between the hardware device HW and the monitoring processing device SW. A monitoring system SYS is formed by the monitoring processing device SW and at least the interface device ID.
As indicated above, the indication registers REG11, . . . , REG1m can be latched or non-latched, and FIG. 4 shows a timing diagram for both cases. The top graph indicates the current state of the hardware device HW. At times t0, t1, t3 a change of the current state of the hardware HW occurs, namely from a state B to a state A at time t0, from a state A to a state B at time t1 and from a state B to a state A at time t3.
In the memory MEM1 state A and state B will respectively be indicated by a particular combination of bits A, B in the individual registers REG11, . . . , REG1m. As is indicated with the middle graph in FIG. 4, a non-latched indication register represents the current status of the hardware device HW, since the state in the non-latched register always follows the state of the hardware device HW. A bit or state in a latched indication register will stay active until it is read by the monitoring processing device SW at time t2, i.e. a reading operation to the memory MEM1 resets a latched indication bit (or latched indication state). The current status can be determined from a latched register or latched memory by reading the register twice at time t2 and t4. For example, if at time t2 the latched register is read out by the monitoring processing device SW two times, then state B is read at second read. This state is identical to the current state of the hardware at that time. If at time t2 the latched register is read out once only, then state A will be read and the register will be reset to state B.
Whilst FIG. 4 only shows the situation when a single process means of the monitoring processing device SW accesses the memory MEM1 (or its respective registers), the monitoring processing device SW can handle the indications in several ways. In particular, the concurrent access SAA, SAB, SAC of several process means A, B, C or even the succeeding access of these process means cause severe problems, i.e. the status information cannot be accurately provided simultaneously and/or successively to said individual process means A, B, C of said monitoring processing device.
Namely, as is indicated in FIG. 3 the process means A, B, C may each use a different polling or clock rate such that the information in the interface device may under some circumstances not be provided accurately to each process means. For example, the process means A may use a clock rate of 100 ms, the process means B a clock rate of 1 minute and the process means C a clock rate of 10 min. It is clear that a collision can then occur in the following four cases.
Firstly, several process means A, B, C may be interested in the current status or the latched status. Then, the access by one process means (e.g. the xe2x80x9cfastestxe2x80x9d process means A) to a latched register obviously destroys the latched status for other supposedly xe2x80x9cslowerxe2x80x9d process means.
Secondly, as explained above, since not all process means may require access to the entire status information, only a part of the entire status information may be provided to an individual process means. That is, several process means may be interested in different bits (parts of the status information) of a register. Then, the access by one process means to the register destroys the latched state for other processes interested in other indication bits of the same register, since the complete status information (in one register or in the memory) is reset even when a single individual indication bit is read.
Thirdly, several process means A, B, C may be interested in the same bit of a register. Then the access by one process means to the register destroys the latched status for other process means interested in the same indication bit.
Fourthly, the entire status information consists of individual parts which may be stored as a sub-set of bits in one register or even as a set of bits distributed (located) in bit positions of several separate registers. Then, an access to many registers is required. That is, assuming that a part of the status information is indicated by a combination of several bits situated at bit position 1 in register REG11, . . . REG12, REG13 the process means has to read three bit positions from three separate registers. This may be done in parallel, but in most applications the SW device can only access one register at a time. So the registers have to be read sequentially, the state of the hardware device might change already such that after reading the bit position 1 at register REG11, the bit located at bit position 1 of register REG13 may already relate to the next status of the hardware device.
Thus, it should be understood that not each process means A, B, C has a need to be provided with the entire status information stored in the memory MEM1, but that some of the process means or all of them may only require an access to a part of the status information located in one register or being assembled from individual parts of several registers.
Despite the process means A, B, C each have their own access means SAA, SAB, SAC which respectively specify which part of the status information is to be read out from the MEM1, there are severe collision problems if several processes A, B, C simultaneously or sequentially access the indication data (the bits) in the memory MEM1, as explained above. One can say that the register structure presented by the interface device ID is not matched to the structure required by the monitoring processing device SW, i.e. the access specification SAA, SAB, SAC used by the individual process means A, B, C. The result is a lower performance (large access times) and complicated structures of the process means with all its consequences of increased processing times and high costs.
It should also be noted that in FIG. 3 the process means A, B, C forming the monitoring processing device SW can be individual processing programs realized in hardware or software. In fact, the complete monitoring processing device SW may be a software SW that contains several processing programs. As explained above, such programs can for example be employed in a multi-tasking environment. However, such processing programs may also be realized by hardware, such that the monitoring processing device is not restricted to a software realization, but also a hardware realization are within the scope of the invention.
As explained above with reference to FIGS. 3, 4, the individual process means A, B, C may have different access requirements, i.e. they must be provided with the status information (or part of it) differently. For example process means A may only be interested in bits 2, 3 in register REG11, whilst process means C may only be interested in the bits stored in the last two registers at bit positions 1, k. However, reading bits 2, 3 by the process means A already resets the status and therefore process means C (having a slower clock rate) cannot access this information again. Also collisions may occur if several process means access one or a number of bits simultaneously.
Therefore, the object of the present invention is
to provide an interface device, a method and a monitoring system such that each one of a plurality of process means can be provided accurately with the status information (or at least a part of it) which it requests according to its access specification.
The interface device, the method and the system of the invention for providing status information about a status of a hardware device to a plurality of process means of a monitoring recessing device comprise a first memory storing a status information about a current status of the hardware device, a plurality of second memories each being accessible by a respective one of the process means and a mapping means for copying at least a part of said current status information stored in said first memory to at least one of said second memories according to a predetermined mapping pattern specifying which part of said current status information is to be copied into which second memory.
According to the invention the interface device comprises a first memory and second memories which are each assigned to a specific process means of the process means in the monitoring processing device. The hardware device writes status information about a status of the hardware device into the first memory. The mapping means copies the status information in the first memory to at least one second memory according to the mapping pattern. Since the first memory and the second memories are decoupled, each process means can be provided with the status information (or a part of it) which it requires. In the simplest case each second memory will contain the complete status information, however, if a process means which runs at a higher polling rate reads the status information from its associated process means, the status information is still available in other memories dedicated to other process means which might run at a lower clock rate. Thus, each process means can independently read and process the status information (or a part of it, which is requests according to its specific needs).
Preferably, the first memory and the second memories each comprise a number of registers and the mapping pattern specifies which part of the first register in the first memory should be copied to specific second registers on the second memories. Thus, even status information which is assembled from different parts of different first registers can be copied to one second memory and can thus individually be provided for the associated process means. The number of the registers in the first memory and the second memories can differ from each other, since some of the process means may require a different part of the status information having a different size. If the number of registers in the first memory and the number of registers in a second memory is the same, then the complete status information from the first memory can be provided to the process means associated with this second memory.
The status information may be stored as individual bits in each register and the mapping pattern predetermines the bit positions, even from several different registers simultaneously, which should together be copied to one second memory (i.e. its respective registers).
A set up means may be provided for setting predetermined mapping patterns in said mapping means. Thus, even when the individual process means are not changed, programs or algorithms for processing the status information may require different parts of the status information at different times. By merely changing the mapping pattern, an immediate provision of this new part of the status information can be provided to the respective process means. Therefore, a flexible assignment of the status information to the individual process means can be achieved.
The mapping means may copy a bit to the second memory as soon as it has been set by the hardware device in the first memory. Thus, some of the second memories may contain an immediate real-time image of the status (or a part of the status) of the hardware device. Alternatively, the mapping means only reads a status information from a first register, if a complete new word (consisting of a predetermined number of bits) has been written into it.
Since the first and second memories are decoupled the respective memories can be of an arbitrary type. For example, the second memory may be of a non-latching type, wherein the process means associated with it can always read the current status information which is copied by the mapping means. Alternatively, the second memories may be of a latching type, such that the state in the second memory is reset after the process means has read the status information therein. Preferably, the first memory is a non-latching memory and said second memories are each latching memories.
Further advantageous embodiments and improvements of the invention may be taken from the dependent claims. Hereinafter, the invention will be explained with respect to its embodiments and with reference to the attached drawings.